Delay correction circuit for semiconductor tester

ABSTRACT

The present invention is to provide a delay correction circuit for a semiconductor tester which can decrease a circuit size and electric power consumption in a timing correction part. To achieve this goal, a variable delay element which corrects the phase difference stemming from the common parts of test stations is provided at an output of a waveform controller. At an output of a waveform output controller which generates the signal determining whether a signal should be applied to the test stations, flip-flops are provided which perform an inter-leave function. A gate circuit is provided which combines each unit of the inter-leave function based on the output signal of the variable delay element. An AND gate is provided which takes the logical AND between the output of the gate circuit corresponding to the test station and the output of the variable delay element. A variable delay element which corrects the phase difference stemming from each test station is provided at the output of the AND gate.

TECHNICAL FIELD

This invention relates to a delay correction circuit for a semiconductordevice tester to correct the timings of signals applied to semiconductordevices under test and to establish a phase relationship between thesignals when a plurality of test stations for are provided to test thesemiconductor devices under test simultaneously by the semiconductordevice tester.

BACKGROUND ART

Generally, a plurality of test stations are used to test and processmany semiconductor devices to be tested efficiently in a semiconductortester. The devices to be tested are electrically connected to the teststations through IC sockets, and the device test proceeds simultaneouslyfor each semiconductor device under test. Waveforms of test signals foreach device under test must be applied in the same condition. Hence, thesemiconductor tester is so composed as to include a timing correctioncircuit for each test station to correct the differences between thetimings of the test signals and synchronizes the phase of the testsignals at each device terminal to be tested.

FIG. 3 shows an example of a delay correction circuit in a conventionalsemiconductor tester. A timing correction part 10 is provided for eachpin of the device to be tested as designated by #1, #2, . . . #n. Anoutput signal of a corresponding pin of the device is taken out as anoutput signal 61 for a test station 1 and an output signal 62 of anotherdevice is taken out for a test station 2. The wave form to be providedto the test station 1 (21) and to the test station 2 (22) is generatedby a waveform controller 11. A signal for determining whether thiswaveform should be provided through a driver terminal to the device isgenerated by a waveform output controller 12. Waveform output controlsignals 51 and 52 for corresponding test stations are adjusted in thetiming at a flip-flop 13 by a timing clock 50, and are taken out assignals 53 and 54. A logical AND is established between a signal fromthe waveform controller 11 and the signal 53 from the flip-flop 13 by anAND gate 14 to produce a signal for the test station 1. Similarly, alogical AND is established between the signal from the waveformcontroller 11 and the signal 54 from the flip-flop 13 by an AND gate 15to produce a signal for the test station 2. The flip-flop noted abovemay be a edge type flip-flop or a latch type flip-flop.

In general, the waveforms generated by the waveform controller 11 differtheir phases with respect to each pin of the device under test. This isbecause the phase differences are caused by the complexity of waveformsprovided to the device to be tested, which in turn necessitates thewaveform controller 11 to have a large number of gate circuits, therebyvary the accumulated propagation delay times of the gate circuits forthe corresponding pins of the device. Hence, variable delay elements(16, 17) are provided at the timing correction part 10 so as to correctthis phase differences between the pins. In addition, the smalldifferences of the delay times occur between the test station 1 and thetest station 2. This is mainly caused by the difference in the cablelengths used in the test stations. Hence, the variable delay elementsare provided at each test station as well. A variable delay element 16for the test station 1 covers both of the two kinds of delay times notedabove. A variable delay element 17 for the test station 2 covers both ofthe other two kinds of delay times noted above.

Assuming an adjustable range stemming from the delay time difference forthe test station 1 as A1, an adjustable range stemming from the delaytime difference of the test station 2 as A2, and an adjustable rangestemming from the delay time difference of the waveform controller as B.Then an adjustable range S1 to be covered by the variable delay element16 for the test station 1 is represented as;

    S1=A1+B

And an adjustable range S2 to be covered by the variable delay element17 for the test station 2 is represented as;

    S2=A2+B

Hence, each variable delay element is composed of the sum of the delaytimes in the timing correction part common to all the test stations andin the timing correction part independent for each test station.

FIG. 4 is a timing chart for explaining the operation of theconventional delay time correction circuit. An output of the waveformcontroller 11 at the timing correction part #1 is in a position behindthe timing clock 50 by a time T15. On the other hand, an output of thewaveform controller 11 at the timing correction part #n is delayed by atime T25 from the timing clock 50.

The output 61 of the delay element 16 at the timing correction part #1is adjusted to a timing T13 to take into consideration of a delay timeT11 in the test station 1 so as to generate the waveform as shown inFIG. 4 at the terminal 71 of the test station 1. Next, the output 62 ofthe delay element 17 at the timing correction part (#1) is adjusted to atiming T14 to take into consideration of the delay time of a delay timeT12 in the test station 2 so as to generate the wave form as shown inFIG. 4 at the terminal 72 of the station 2 with exactly the same phaseas the terminal 71.

Similarly, the output 61 of the delay element 16 at the timingcorrection part #n is adjusted to a timing T23 to take intoconsideration of a delay time T21 in the test station 1 so as togenerate the waveform shown in FIG. 4 at the terminal 73 of the teststation 1. Next, the output 62 of the delay element 17 at the timingcorrection part #n is adjusted to a timing T24 to take intoconsideration of a delay time T22 in the test station 2 so as togenerate the waveform at the terminal 74 of the test station 2 withexactly the same phase as that of the terminal 73 of the test station 1.

In the foregoing example, the timing value in the common correction part(the difference between timings T15 and T25) accounts for thesignificant portion of the delay time to be adjusted, while delay times(T11, T12, T21, T22) in the correction part at each test stationoccupies a small portion of the delay time. Accordingly, the delay timecorrection circuit in the timing correction circuit 10 requires acircuit size which is about twice as large as that required in thecommon correction part. Hence the conventional technology requires alarge circuit size and thus a large electric consumption.

Therefore, It is an object of the present invention to solve the abovenoted problems in the conventional delay correction circuit of thesemiconductor tester. It is a further object of the present invention toprovide a delay correction circuit for a semiconductor tester whosetiming correction part is composed of a correction circuit which iscommon to all the test stations and an independent correction circuitfor each test station to decrease the circuit size and the powerconsumption.

DISCLOSURE OF THE INVENTION

In the timing correction circuit of the present invention for thesemiconductor device tester having a plurality of test stations formounting the semiconductor devices to be tested, a variable delayelement which corrects the phase difference stemming from a common partof the test stations is provided at an output side of a waveformcontroller which generates waveform signals. Flip-flop circuits whichperforms inter-leave functions by a waveform control signal are providedat an output side of a waveform output controller which generates asignal for determining whether the waveform signals be applied to thecorresponding test station. Gate circuits are provided which combineseach element of the inter-leave functions by the output signal of thevariable delay element. Further, an AND gate is provided which takes thelogical product between an output signal of the gate circuit for eachtest station and an output signal for the variable delay element.Variable delay elements are further provided which correct phasedifferences stemming from each test station at the output of the ANDgate. The delay correction circuit of the present invention for thesemiconductor tester is configured as mentioned above for all the teststations.

According to this invention, each waveform to be applied to thesemiconductor device under test is combined after the wave controlsignal is inter-leaved by the output signal of the waveform controllerand has passed the common correction circuit having the variable delayelement. Then the phase differences in the waveform stemming from eachstation are corrected by the variable delay element in each teststation. Hence, concerning the circuit size of the timing correctionpart, the common correction circuits do not need to be as many as thenumber of the stations, but only one common correction circuit issufficient. Hence the circuit size is greatly decreased.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the embodiment of the presentinvention.

FIG. 2 is a time chart showing the operation of the timing correctionpart of the present invention.

FIG. 3 shows an example of a conventional delay correction circuit in asemiconductor tester.

FIG. 4 is a timing chart for explaining the operation of theconventional delay correction circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention is explained in the followingwith reference to the drawings. FIG. 1 is a block diagram showing anembodiment of the present invention. As shown in FIG. 1, the outputs(53, 54), which are provided from a waveform output controller 12 aresynchronized with each other by a the flip-flop 13. The outputs 53 and54 are latched by flip-flops (221, 222) using a waveform generationclock from a waveform controller 11. In this example, two latches areused to perform a two phase inter-leave function.

A flip-flop 200 outputs two signals which alternately change the statefor every input of the clock signal. At gates 211 and 212, the outputclock from the waveform controller 11 is selected based on the state ofthe output signal from the flip-flop 200, and the selected signal isprovided to a flip-flop 221 and a flip-flop 222 as a clock signal. Theflip flops 221 and 222 alternately latch and hold the input data.

The signal from the waveform controller 11 is delayed by a variabledelay element 100. The amount of the adjustable delay time of thevariable delay element 100 is determined to a value sufficient to coverthe time differences in the correction factors common to all the teststations. Thus, the adjustable delay time corresponds to theaforementioned adjustable range B derived from the delay time differenceof the waveform controller. The data held by the flip-flop (221, 222) ismaintained even after the delay time determined by the variable delayelement 100. In the end, waveforms to be provided for each test stationare combined by gate circuits 411 and 412. A flip-flop 300 generates twooutput signals which alternately change the state corresponding to thetwo phase inter-leave function. Based on the output signals of theflip-flop 300, a first phase signal is selected by a gate circuit 311,and a second phase signal is selected by a gate circuit 321, and alogical sum of both of the selected phase signals is produced by an ORgate 331 as a waveform control signal for the test station 1. Similarly,a first phase signal is selected by a gate circuit 312, a second phasesignal is selected by a gate circuit 322, and a logical sum of both ofthe selected phase signals is produced by an OR gate 332 as a waveformcontrol signal for the test station 2.

The output signal of the gate circuit 411 is provided to the teststation 1 through a variable delay element 421. The adjustable range ofthis variable delay element 421 is determined to be sufficient to coverthe delay time differences in the test station 1. This range correspondsto the adjustable range A1 described above. Similarly, the output signalof the gate circuit 412 is provided to the test station 2 through avariable delay element 422. The adjustable range of this variable delayelement 422 is determined to be sufficient to cover the delay timedifferences in the test station 2. This range corresponds to theadjustable range A2 described above.

FIG. 2 is a timing chart showing the operation of the timing correctionpart of the present invention. In FIG. 2, the delay time by the variabledelay element 100 is represented as T100. The delay time of the output61 by the variable delay element 421 for the test station 1 isrepresented as T421. The delay time of the output 62 by the variabledelay element 422 for the test station 2 is represented as T422.

Since the adjustable delay amount of each variable delay element (100,421, 422) is determined as described above, the adjustable range of thevariable delay element 421 can be small to correct only the timedifference stemming from the test station 1. The adjustable range of thevariable delay element 422 can be small to correct only the timedifference stemming from the test station 2. The variable delay element100 is a common correction circuit and is required to have a largeadjustable rage to correct the time difference stemming in the waveformcontroller. However, in the timing correction part 10, only one suchvariable delay element is needed. Therefore, when the comparison ismade, a circuit scale SS of the conventional timing correction circuitis represented as;

    SS=(A1+B)+(A1+B)=A1+A2+2B

while a circuit scale SS of the present invention is represented as;

    SS=A1+A2+B

Thus, it is possible to greatly reduce the circuit scale. Even when thenumber of the station is arbitrarily assigned as n, only one commoncorrection circuit is sufficient, thereby minimizing the circuit scale.

The embodiment described above is composed of the two phase inter-leavefunction. Generally, the number of the latch circuits is determined bythe relationship between the minimum spacing between the clock signalgenerated by the waveform controller and the maximum delay amount of thevariable delay element 100. Thus, the number of the flip-flops (221,222) for the latch circuits can be increased to compose a multi-phaseinter-leave function.

INDUSTRIAL APPLICABILITY

Since it is configured as described in the foregoing, the presentinvention has the following effects. In the delay correction circuit fora semiconductor tester, the timing correction part, which has beenconventionally provided in each of the test stations, is now composed ofa combination of a common correction circuit and a correction circuitfor the corresponding test station. Thus, the delay correction circuitof the invention is possible to decrease the circuit size and theelectric consumption.

What is claimed is:
 1. A delay correction circuit for a semiconductortester having a plurality of test stations for mounting semiconductordevices to be tested thereon, characterized in having:a variable delayelement (100) provided at an output side of a waveform controller (11);flip-flops (200, 221, 222) provided at an output of a waveform outputcontroller (12) for performing an inter-leave function based on awaveform control signal from the waveform output controller; gatecircuits (311, 321, 331, 312, 322, 332) which combine elements of theinter-leave functions based on output signals from the variable delayelement (100); and an AND gate (411) which produces a logical ANDbetween an output of the gate circuit (331) corresponding to the teststation n and an output of the variable delay element (100).
 2. A delaycorrection circuit for a semiconductor tester of claim 1 characterizedin minimizing a circuit size for all of the test stations by providingan variable delay elements (421, 422) at outputs of the AND gates (411,412) for the test station n.
 3. A delay correction circuit for asemiconductor tester of claim 1 or 2 characterized in having:a flip-flop(200) which alternately outputs m states for every clock from thewaveform controller (11); a gate circuit (211, 212) which selects aclock signal from the waveform controller (11) based on the m states;and flip-flops (221, 222) which latch the signal from the waveformoutput controller (12) by the selected outputs of the gate circuit (211,212).
 4. A delay correction circuit for a semiconductor tester of claim1 or 2, wherein the gate circuit having each unit of the inter-leavefunction characterized in having:a flip-flop (300) which alternatelyoutputs m states for every clock from the variable delay element (100);a gate circuit (311, 321, 312, 322) which selects each output signalfrom the flip-flop (221,222) based on the m states; and an OR gate (331)which outputs a logical sum of the outputs of the gate circuit (311,321).